Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

Hiew, Fu San (2006) Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA. Masters thesis, Multimedia University.

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Abstract

In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment, in which it can reduce the coding lengthiness.

Item Type: Thesis (Masters)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 19 Aug 2010 08:21
Last Modified: 19 Aug 2010 08:21
URI: http://shdl.mmu.edu.my/id/eprint/1207

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