Power Efficiency Top-Down ALU for Error Correction and Detection Circuit


Senthilpari, Chinnaiyan and Diwakar, K. and Deivasigamani, Subbramania Pattar and Velrajkumar, P. and Ayavoo, Rajenthyran (2022) Power Efficiency Top-Down ALU for Error Correction and Detection Circuit. In: 2022 3rd International Conference on Communication, Computing and Industry 4.0 (C2I4), 15-16 Dec 2022, Bangalore, India.

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Adder circuits and other logic blocks are used in the design of the ALU circuit. The primary goals of this study were to improve the efficiency of a 1-bit ALU and to speed it up without significantly increasing its power consumption. Both the Shannon theorem and mixed Shannon are used in the design of the proposed top-down ALU. Moreover, this article suggested utilising not one but three distinct ALUs: Binvert, Bit Slice, and MIPS. Compared to previously published circuits, the calculated values of power dissipation, propagation latency, and area are all improvements thanks to the simulation results. The proposed circuit is weighed against others that the adder-based ALU model could employ in artificial intelligence (AI)/Expert Systems (ES), Quantum Computing (QC), and Bio-Computing (BC) using parallel processing circuit blocks. When calculating the proposed adder-based ALU circuit's throughput, latency, and EPI, a BSIM4 analyser is used, which provides high throughput and lower latency than reportedfindings due to taking all the care off).

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Top-down ALU , Shannon theorem , Throughput , Latency , Power Dissipation , Propagation Delay , Area , EPI
Subjects: Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 28 Mar 2023 06:50
Last Modified: 28 Mar 2023 06:52
URII: http://shdl.mmu.edu.my/id/eprint/11278


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