High-Performance CMOS Clock And Data Recovery Circuit


Tan, Kok Siang (2006) High-Performance CMOS Clock And Data Recovery Circuit. Masters thesis, Multimedia University.

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In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption.

Item Type: Thesis (Masters)
Subjects: Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science > QA76.75-76.765 Computer software
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 05 Aug 2010 03:38
Last Modified: 05 Aug 2010 03:38
URII: http://shdl.mmu.edu.my/id/eprint/1094


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