Design of SRAM for Wireless Sensor Networks using Energy Efficient and Variability Resilient Techniques


Thirugnanam, Sargunam and Lim, Way Soong and Prabhu, Chinnaraj Munirathina (2022) Design of SRAM for Wireless Sensor Networks using Energy Efficient and Variability Resilient Techniques. In: 2nd FET PG Engineering Colloquium Proceedings 2022, 1-15 December 2022, Multimedia University, Malaysia. (Unpublished)

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Background In modern days, wireless sensor network has received attention of the researchers due to its applications in military surveillance, environment monitoring, health monitoring, industrial monitoring etc. The memory has become the major portion of these modern architectures. SRAM is a key component of the processing system of sensor nodes. The on-chip SRAM cache consumes a major portion of the total dynamic power per operation. Therefore, the design of energy efficient SRAM is important requirement to enable the further development of energy limited wireless sensor networks. Purpose The power efficient, process and variability tolerant SRAM is a critical requirement in modern low power applications. This aim is to present an energy efficient SRAM memory with enhanced variability tolerance against process, voltage, temperature (PVT). A 32 Kilobit array has been designed using the energy efficient SRAM cell together with peripheral circuits. Design/Methodology/Approach There are 3 SRAM cells have been designed namely Process Tolerant and Power Efficient SRAM 11T cell (PTPE11T), Low Power Robust 13T SRAM cell (LPR13T) and Energy Efficient and Variability Resilient SRAM 11T cell (E2VR11T). All the cells are designed with a unique technique known as Data Aware Read-Write Assist (DARWA). The DARWA technique employs separate read and write circuits. The single ended read circuit is used for significant read operation independently. The latch property of the inverter is dynamically used to perform faster switching during the write operation. Hence, the read and write conflict is completely removed. The proposed E 2VR11T cell is designed with 11 Transistors and implemented in 45nm CMOS technology. The separate read circuit reduces the read power and improves the read stability. The schematic diagram of the proposed E 2VR11T cell is shown in the Fig. 1 and the Layout is shown in Fig.2. The status of control signals for write, read and hold state is presented in Tab. 1. The cell is compared with 6 other cells in terms of power, stability, temperature, supply and threshold voltage, read/write behaviours in the PVT conditions. The robustness of the cells is evaluated with different PVT variations. The E 2VR11T cells has been optimized and used to design the 32Kb array which is also been simulated for power and delay.

Item Type: Conference or Workshop Item (Other)
Uncontrolled Keywords: SRAM Cell, WSN, Power, Delay, PVT, Stability, SNM, Memory cache, Peripheral circuits
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 16 Feb 2023 08:32
Last Modified: 16 Feb 2023 08:32


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