Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors


Singh, Ajay Kumar and Tan, Chun Fui and Tan, Wilson Wee Xin (2020) Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors. International Journal of Electrical and Computer Engineering (IJECE), 10 (2). pp. 1764-1771. ISSN 2088-8708

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In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Item Type: Article
Uncontrolled Keywords: Tunnel field-effect transistors, hetero-gate dielectric, poisson equation, TFET, threshold voltage, tunneling width
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7871 Electronics--Materials
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 14 Dec 2020 16:18
Last Modified: 14 Dec 2020 16:18


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