Design of High Performance FinFET SRAM Cell for Write Operation


Sargunam, T. G. and Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2019) Design of High Performance FinFET SRAM Cell for Write Operation. In: Emerging Trends in Computing and Expert Technology. Lecture Notes on Data Engineering and Communications Technologies, 35 . Springer, Cham, pp. 908-914. ISBN 978-3-030-32149-9, 978-3-030-32150-5

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A novel FinFET based SRAM cell is proposed to reduce the dynamic power consumption during write mode in this research work. The proposed High Performance FinFET SRAM (HPFS) cell consists of 8-Transistors instead of 6-Transistors as in conventional SRAM cell. The extra two transistors are used to reduce the write power during transition. The proposed circuit is simulated for Microwind EDA tool. The results of HPFS cell is compared with conventional SRAM cells. From the simulated results, it has been observed that the suggested HPFS cell consumes lower power and provides lower access delay compared to other cells.

Item Type: Book Section
Uncontrolled Keywords: Static random access memory, FinFET, High performance, Low power, SRAM cell, Power consumption, Low power and access delay
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 08 Dec 2020 17:31
Last Modified: 08 Dec 2020 17:31


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