A Programmable CMOS Delay Line for Wide Delay Range Generation and Duty-Cycle Adjustability


Abdulrazzaq, Bilal I. and Abdul Halin, Izhal and Lee, Lini and M. Sidek, Roslina and Md. Yunus, Nurul Amziah (2017) A Programmable CMOS Delay Line for Wide Delay Range Generation and Duty-Cycle Adjustability. Pertanika Journal of Science & Technology, 25 (S). pp. 123-132. ISSN 0128-7680

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A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2μs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13μm Silterra CMOS technology. The active layout area is (101 x 142) μm2, and the total power consumption is only 0.1 μW.

Item Type: Article
Uncontrolled Keywords: CMOS delay line, synchronous counter, latches, delay element, delay range, duty cycle, linearity, PVT variations
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7871 Electronics--Materials
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 21 Oct 2020 20:33
Last Modified: 21 Oct 2020 20:33
URII: http://shdl.mmu.edu.my/id/eprint/7030


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