Modified SR latch in dynamic comparator for ultra-low power SAR ADC


Sharuddin, Iffa and Lee, Lini (2015) Modified SR latch in dynamic comparator for ultra-low power SAR ADC. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS). IEEE, pp. 151-154. ISBN 978-1-4799-1731-0

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A low power dynamic comparator for Successive Approximation (SAR) analog-to-digital converter (ADC) is presented. The modified dynamic comparator is designed to be implemented in the ultra-low power Successive Approximation Analog to Digital Converter (SAR ADC). The improved comparator has advantages of smaller resolution and stable output voltage for SAR ADC operation by using modified SR Latch compared to previous works reported. The proposed dynamic comparator is designed and simulated in the 0.18 μm CMOS process. Simulation results show that it only consumed 191 pW at 1.5 V power supply with clock frequency of 0.1 MHz. Both pre and post layout has been simulated and the performance analysis is presented.

Item Type: Book Section
Uncontrolled Keywords: Ultra-low power, Dynamic Comparator, Analog-to-digital converter, Successive approximation
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 13 Dec 2017 16:41
Last Modified: 13 Dec 2017 16:41


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