Accelerating video and image processing design for FPGA using HDL coder and simulink

Chan, Jerry Ting Hai and Ooi, Chee Pun and Tan, Wooi Haw (2016) Accelerating video and image processing design for FPGA using HDL coder and simulink. In: 2015 IEEE Conference on Sustainable Utilization And Development In Engineering and Technology (CSUDET). IEEE Xplore, pp. 1-5. ISBN 978-1-4799-8612-5

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Official URL: http://doi.org/10.1109/CSUDET.2015.7446221

Abstract

Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as FPGA. The design process traditionally uses Verilog and VHDL for synthesizing and validating the hardware. These design process are technically complex and time consuming. In this paper, we present an alternative approach using a model based design framework based on HDL Coder, Vision HDL Toolbox and Simulink to accelerate the design of video and image solution. Several important issues in this framework are discussed namely, Pixel Streaming Design, Co-simulation and FPGA in the Loop (FIL). Based on this framework, a video of human walking are processed to extract out two features which are the human height and edge. The design is implemented in an Altera DE2-115 FPGA board. The goal of this paper is to tackle the technical complexity and reduce development time of traditional FPGA design.

Item Type: Book Section
Uncontrolled Keywords: Feature extraction, FPGA, video processing, HDL Coder, Simulink, Vision HDL Toolbox, Model Based Design, Co-Simulation, FPGA in the Loop, Pixel Streaming Design
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK5101-6720 Telecommunication
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 21 Feb 2017 08:32
Last Modified: 21 Feb 2017 08:32
URI: http://shdl.mmu.edu.my/id/eprint/6467

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