Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

C., Senthilpari (2009) Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach. PhD thesis, Multimedia University.

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Abstract

This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder circuit is designed completely by using the Shannon theorem. The Mixed-Shannon and full Shannon adder cells are used in the implementation of 8-bit array multipliers, namely, the Braun array, CSM and Baugh-Wooley multipliers. Output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulation results.

Item Type: Thesis (PhD)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Users 27 not found.
Date Deposited: 11 Jan 2011 03:57
Last Modified: 11 Jan 2011 03:57
URI: http://shdl.mmu.edu.my/id/eprint/1786

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