Fast-Lock Low -Jitter Delay Locked Loop


Soh, Lip Kai (2007) Fast-Lock Low -Jitter Delay Locked Loop. Masters thesis, Multimedia University.

Full text not available from this repository.


In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.

Item Type: Thesis (Masters)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 19 Aug 2010 05:56
Last Modified: 19 Aug 2010 05:56


Downloads per month over past year

View ItemEdit (login required)